The related technologies of computer and microcomputer design have made incredible advances in the past several decades. New architectural ideas combined with advances in integrated circuit technology have created a series of machines which achieve remarkable performance results.
One way that computer architects and designers can further improve the performance of their machines is by creating an apparatus or mechanism for stopping a processor regardless of the current instruction it is executing. Stopping a processor's operation is useful, for example, when testing the state of the processor. One of the problems that has plagued previous technologies is that a processor's state could only be tested, and therefore guaranteed to be valid, when the internal clock signal was stopped and certain predetermined conditions were satisfied. By way of example, such conditions usually occurred during a HALT state or during an input/output (I/O) read. Under these conditions, the processor's state was known, so that the processor could be tested at that point. The problem with this prior art approach, however, is obvious; namely, that testing a processor only when a certain number of predetermined conditions are satisfied is highly impractical.
The alternative to stopping a processor on predetermined conditions is to stop the processor asynchronously by disabling the externally-generated signal used as a reference to generate the internal clock rate of the device. The drawback to stopping the processor asynchronously in this manner is that the processing unit is very often in the middle of executing one of its instruction. In the middle of an instruction or micro-instruction, both internal and external buses are precharged. Stopping the processor in the middle of a bus cycle discharges the bus, with a resultant loss of the information being transferred.
Another problem with asynchronously disabling the external reference frequency generator involves the fact that most microprocessors and computer systems utilize a phase-locked loop (PLL) circuit to multiply the reference frequency by some factor to generate the system's internal clock rate. The internal clock signal is utilized by the central processing unit (CPU) of the computer during the execution of its various functions and instructions. The problem arises that if the clock is stopped externally, then the internal phase-locked loop circuitry is likewise disabled. Under such circumstances, re-enabling the external reference frequency does not produce an instantaneous response from the PLL; that is, the PLL requires some fixed time period (e.g., several hundred milliseconds) to stabilize. During this start-up time period, spurious signals and glitches are commonly generated, leading to unpredictable results. Thus, starting and stopping of the processor's clock by disabling the external reference input frequency results in a loss of psuedo-instantaneous response.
What is needed then is a means for stopping the CPU's clock at any time, regardless of the instruction that the processor is presently executing, while guaranteeing that the processor is in a known state. As will be seen, the present invention allows the user to stop the clock of a processor within a computer system asynchronously, while still guaranteeing that the state of the processor is preserved. Guaranteeing the processor's environment just previous to stopping the processors clock allows the device to be tested in a manufacturing environment. Another advantage of the present invention is that the processor can be re-enabled without having to restart the system's PLL circuitry. This obviates the need to otherwise wait an inordinate length of time for a stable clock signal to be generated.